The present invention relates to the field of image processing. More specifically, the present invention relates to methods and apparatus for concatenating data words from a bitstream. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. This implementation is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the xe2x80x9cBlue Bookxe2x80x9d), by the Joint Photographic Experts Group (the JPEG standard), and by the Motion Picture Experts Group (the MPEG standard).
An encoded digital video bitstream is a very long combination of zeroes and ones. In order to better store these values, each set of 16 bits are packed into one word. The key issue in the decoding process is that it is a recursive operation, where the next result will depend on the current result. In other words, the point at which a first word ends must be known, in order to know where the next word begins. Thus, without knowing the present word boundaries, it will be infeasible to predict the next word""s boundary and so identify that word. That means parallel execution of decoding is not feasible with limited gate counts.
What is therefore required is a bit selection apparatus that provides fast efficient concatenation of bits to form words. Moreover, a technique of this type should support the concatenation of bits in words with bits that are not properly justified, on a word-to-word basis. Preferably, this implementation should be relatively small in terms of area required when implemented in an integrated circuit. Finally, the implementation should provide an acceptable level of computational accuracy (and so image quality).
The present invention solves the problems associated with the prior art by providing a method and apparatus for efficiently and accurately concatenating data words from a bitstream.
According to the present invention, the input word may be partial word whose length is smaller than 16-bits. A second subtractor is used to keep track of bits remaining in sel[15:0]. A bit-selector is also used. The bit selector is implemented using random-logic with extended selection range (48-bit inputs).
According to the present invention, whenever a block stops decoding without an EOB token being found, it will store the last-received, right aligned 16-bit word in the scratch memory. Otherwise, if the block is finished, the left-aligned 16-bit word found in sel[15:0] will be stored into the scratch memory, shown as memory attached to the video decoder in FIG. 1. In the second or the third pass, the unfinished block will put the right aligned word in prev[15:0] and put the left-aligned word which is read from scratch memory in next[15:0].
These and other embodiments of the present invention, as well as its advantages and features are described in more detail in conjunction with the text below and attached figures.